Electronic devices in recent years include circuits operating with various operation voltages, and achieves less power consumption and downsizing. For an operation of each of the electronic devices thus including the circuits different in operation voltage, a level shift circuit is employed to switch a voltage level of a logic signal.
Regarding the level shift circuit, for example, Japanese Patent Laying-Open No. 2004-343396 (Patent Document 1) discloses an art of handling penetration current generated when a PMOS (positive channel Metal Oxide Semiconductor) transistor and an NMOS (negative channel Metal Oxide Semiconductor) transistor are simultaneously turned on during transition in data input, the PMOS transistor and the NMOS transistor being disposed in series between a power supply and a ground in a level shift circuit. Japanese Patent Laying-Open No. 2004-112666 (Patent Document 2) discloses an art of preventing power consumption from being increased due to penetration current even when one of two power supply voltages supplied becomes unstable in a level shift circuit. Japanese Patent Laying-Open No. 2004-153446 (Patent Document 3) discloses an art of reducing an area occupied by a level shift circuit.